In many data communication applications, serializer and de-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates frequency-dependent signal loss from the communications channel (the signal path between the two end points of a serial link), as well as signal dispersion and distortion, can occur. Ideally, without noise, jitter, and other loss and dispersion effects, a data eye at the receiver will exhibit a relatively ideal shape. In practice, the shape of the data eye changes with noise, jitter, other loss and dispersion effects, and temperature and voltage variations. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal.
Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality. Equalization may also be employed at the transmit side to pre-condition the signal. Equalization, a form of filtering, generally requires some estimate of the transfer function of the channel to set its filter parameters. However, in many cases, the specific frequency-dependent signal degradation characteristics of a communications channel are unknown, and often vary with time. In such cases, an equalizer with adaptive setting of parameters providing sufficient adjustable range might be employed to mitigate the signal degradation of the signal transmitted through the communications channel. Equalization might be through a front end equalizer, a feedback equalizer, or some combination of both. The shape of the data eye also changes due to equalization applied to input signal of the receiver. In some systems, equalization applied by a transmitter's equalizer further alters the shape of the eye from the ideal.
If a simple, analog front-end equalizer (AFE) is employed, the data eye operating margin improves. However, better performance might be achieved through use of a Decision Feedback Equalizer (DFE) in combination with an AFE. Classical DFE equalization optimizes for an ISI and opens up the vertical and horizontal data eye opening. DFE filters play an important role in SerDes communication channels. The DFE filtering is employed to cancel post-cursor inter symbol interference (ISI) in the equalized channel's pulse response. The output of a DFE filter is subtracted from an input signal; The DFE filter includes a number of taps, which number determines how well the post-cursor ISI might be cancelled. The longer the filter length (i.e., the more filter taps), the more ISI terms might be cancelled, but at the expense of increasing DFE filter length complexity and power consumption of a given implementation. Typically, the DFE coefficients are automatically adjusted with adaptive algorithms such as least mean square (LMS). In high speed applications the data path equalization components are most often implemented as analog, transistor level circuits and the adaptation is implemented as digital blocks.
An alternative approach implements only an ADC as an analog circuit, and all other processing of the received signal is implemented fully in the digital domain. Such DSP data path offers better reliability, testability and flexibility, but presents implementation challenges due to lower clock speeds available in digital designs, leading to a need for greater parallelization of the DSP processing.
One of the main equalization components, the DFE, is particularly difficult to parallelize due to its inherent feedback structure.
In a fully digital SerDes receiver the equalization data path is fully implemented as digital blocks and typically follows a Variable Gain Amplifier (VGA) and an Analog to Digital Converter (ADC) at the input. A typical digital data path comprises a Feed Forward Equalizer (FFE), a DFE and adaptation and calibration circuits. For a digital implementation, the clock frequencies available in the receive data path would be an order of magnitude, for example 8-16×, lower that in case of the analog datapath equalization. To maintain the data rate through the receiver, the receiver data path is parallelized by the same factor (8-16×). DFE implementations do not parallelize efficiently due to the need of an immediate feedback from the previous bit to the next bit of processed data. To address this architectural feature in parallel implementations of the DFE, an unrolling technique may be used, but this yields prohibitively large designs for practical applications, scaling exponentially with the number of tap coefficients. For 6-10 DFE taps needed, the size/power cost is prohibitive.
In order to avoid the huge size/power penalty of a large parallelized DFE, a Feed Forward Equalizer (FFE) might be used in place of a traditional DSP-implemented DFE, or in addition to a DFE with fewer taps, making the data path easier to parallelize and implement for very fast data rates. In order to cover all the significant ISI contributing positions in a given channel the delay line of the FFE might typically span several tens of signal samples (symbols) e.g., 40-50 samples). A parallel FFE implementation having several taps on such a long delay line is relatively complex, and has high power consumption.